Nov 06, 2009 (Close-Up Media via COMTEX) --
Mentor Graphics outlined its strategy and roadmap to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, low-power, mixed-signal systems-on-chip (SOCs).
As part of this strategy, Mentor is uniting its embedded compression and automatic test pattern generation (ATPG) technology with the built-in self-test (BIST) technology from recently acquired LogicVision into a new product line, called Tessent. The Tessent line is a comprehensive set of design-for-test and silicon test solutions, and also includes LogicVision's SiliconInsight product, Mentor's layout-aware diagnosis tools and the newly announced Tessent YieldInsight product to provide solutions for post-silicon test characterization and yield analysis.
"Those who follow Mentor Graphics know that we target segments where we can be in a strong number one position," said Joseph Sawicki, vice president and general manager for the Design-to-Silicon Division at Mentor Graphics. "The combination of Mentor's market-leading scan-based test and yield analysis products, and the LogicVision BIST solutions, puts us in the top spot across the board in silicon test. We plan to grow from that position of strength by taking the newly branded Tessent line broader and deeper, and continuing to provide the industry's most complete and unified solution for silicon test, diagnosis and yield analysis."
"ON Semiconductor is committed to utilizing best-in-class ATPG and BIST technologies for product development," said Peter Zdebel, senior vice president and CTO at ON Semiconductor. "We are enthusiastic about the benefits that the single integrated product line from Mentor Graphics offers. We have a longstanding relationship with Mentor in the DFT/ATPG arena that we value and will continue to foster. We look forward to utilizing Mentor's expanded silicon test and yield analysis product-line to provide our customers with world-class products."
((Comments on this story may be sent to newsdesk@closeupmedia.com))
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Tags: graphics market new product president product development products semiconductors technology yield
Companies: LogicVision, Inc. (LGVND), Mentor Graphics Corp. (MENT)
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Nov 07, 2009 (Close-Up Media via COMTEX) --
Mentor Graphics announced that Juniper Networks has completed the world's first network instruction set processor IC using Mentor Graphics physical verification and silicon test tools.
Juniper said its new processor is part of Juniper's latest Junos Trio chipset that enables the delivery of Juniper's MX-3D platforms.
"We went with the Calibre verification platform because it gives a high level of confidence in the manufacturability of our design," said Debashis Basu, senior director of Foundation Technologies at Juniper Networks. "With a design of this size, we needed a solution that could deliver fast turnaround time. The Calibre user interface environment and scripting capability helped us to find and debug problems quickly, and automate chip assembly."
Juniper employed a combination of Mentor's embedded deterministic test pattern generation and memory BIST products to meet demanding test requirements. With hundreds of separate embedded memories, Juniper's design presented a real test challenge to minimize routing congestion, enable at-speed testing, and keep real estate required for BIST controllers to a minimum. Juniper was able to achieve their objectives using Mentor's modular test flow, embedded deterministic pattern compression, and memory BIST technology.
((Comments on this story may be sent to newsdesk@closeupmedia.com))
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Tags: environment foundation products real estate technology
Companies: Juniper Networks, Inc. (JNPR), Mentor Graphics Corp. (MENT)
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Nov 06, 2009 (SmarTrend(R) Research Reports via COMTEX) --
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Tags: graphics market nasdaq research securities trial
Companies: Mentor Graphics Corp. (MENT)
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WILSONVILLE, Ore., Nov 03, 2009 (BUSINESS WIRE) --
Mentor Graphics Corporation (NASDAQ:MENT) today announced that Juniper
Networks has completed the world's first network instruction set
processor IC using Mentor Graphics(R) physical verification and
silicon test tools.
Juniper's new processor is part of Juniper's latest Junos(R)
Trio chipset that enables the delivery of Juniper's MX-3D platforms. "We
went with the Calibre(R)
verification platform because it gives a high level of confidence in
the manufacturability of our design," said Debashis Basu, senior
director of Foundation Technologies at Juniper Networks. "With a design
of this size, we needed a solution that could deliver fast turnaround
time. The Calibre user interface environment and scripting capability
helped us to find and debug problems quickly, and automate chip
assembly."
Juniper employed a combination of Mentor's embedded deterministic test
pattern generation and memory BIST products to meet demanding test
requirements. With hundreds of separate embedded memories, Juniper's
design presented a real test challenge to minimize routing congestion,
enable at-speed testing, and keep real estate required for BIST
controllers to a minimum. Juniper was able to achieve their objectives
using Mentor's modular test flow, embedded deterministic pattern
compression, and efficient memory BIST technology.
"Mentor Graphics is focused on providing solutions that meet the newest
challenges our customers are facing at advanced IC technology nodes,"
said Joseph Sawicki, vice president and general manager for the
Design-to-Silicon division at Mentor Graphics. "For physical design
verification, testing and DFM, our goal is to deliver best-in-class
technology through integrated platforms that also provide maximum
flexibility to adapt to each customer's unique requirements and design
flows."
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in 1981,
the company reported revenues over the last 12 months of about $800
million and employs approximately 4,425 people worldwide. Corporate
headquarters are located at 8005 S.W. Boeckman Road, Wilsonville,
Oregon, 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics and Calibre are registered trademarks of Mentor
Graphics Corporation. All other company or product names are the
registered trademarks or trademarks of their respective owners.)
SOURCE: Mentor Graphics Corporation
Mentor Graphics
Gene Forte, 503-685-1193
gene_forte@mentor.com
Sonia Harrison, 503-685-1165
sonia_harrison@mentor.com
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Tags: consulting corporate electronics environment foundation graphics nasdaq oregon president products real estate semiconductors software technology world wide web
Companies: Juniper Networks, Inc. (JNPR), Mentor Graphics Corp. (MENT)
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