Implied chaos & sound circuits of Ciat-Lonbarde

blog.makezine.com | Jun 28, 2008

Peter Blasser is President and Designer of the electronic instrument producing entity known as Ciat-Lonbarde. The device plans on their site display a refreshing ability for incorporating chance and forcing experimentation - evidenced by instructions from the Paper Circuits...

http://blog.makezine.com/archive/2008/06/implied_chaos_sound_circu.html?CMP=OTC-0D6B48984890

Critical clock-domain-crossing bugs

www.electronicsweekly.com | Apr 21, 2008

Awareness of CDC issues, along with the use of good design practices and proven EDA tools for CDC verification, can avoid costly silicon re-spins and significantly improve time to market.

http://www.electronicsweekly.com/Articles/2008/04/21/43570/critical-clock-domain-crossing-bugs.htm

Critical clock-domain-crossing bugs

www.edn.com | Apr 2, 2008

Awareness of CDC issues, along with the use of good design practices and proven EDA tools for CDC verification, can avoid costly silicon re-spins and significantly improve time to market.

http://www.edn.com/article/CA6544743.html

Asynchronous FIFO-Clock Generation Using DCM

asic-soc.blogspot.com | Jan 1, 2008

<p class="MsoNormal"><b><span><span>Clock Generation using Digital Clock Manager (DCM)</span></span></b></p><div> </div><div> </div><p class="MsoNormal"> </p><span> Note: Diagram numbers are continued from the<span> </span><a

http://asic-soc.blogspot.com/2007/12/asynchronous-fifo-clock-generation.html

Programmable Logic DesignLine | An interesting Gray code FIFO counter question

One way to implement these pointers would be as binary counters. The problem here is that multiple bits may change when transitioning from one value to another. For example, four bits change when when the pointer transitions from 7 to 8 (0111 to 1000 in binary).

http://www.pldesignline.com/199701541;jsessionid=CVEXALF4ZJWOQQSNDLQCKIKCJUNN2JVN?printableArticle=true

CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 (Rev. D

www.rapidonline.com

5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description

http://www.rapidonline.com/netalogue/specs/83-0900.pdf

OUTLINE

LD-1 COURSEWARE Digital Electronics for the LD-1 OUTLINE chapter 1: logic families chapter 2: the basic gates experiment 1: AND gate experiment 2: OR gate chapter 3: the transistor experiment 3: transistor as a switch chapter 4: logic gate from transistor experiment 4: NAND gate experiment 5: NOR

http://www.eandl-global.co.uk/ld1digital.htm

Compagnie del Compteurs (FR) Type A; flight data Type B; (light data and speech Compagnie:...

www.flightglobal.com

Compagnie del Compteurs (FR) Type A; flight data Type B; (light data and speech Compagnie: Induitrielle des Telecommunications (FR) ENB 286; communication Conrac(US) Model 580 T9; digital adaptive recording system; flight data Davall(UK) Type 1050; flight data (recorder only)

http://www.flightglobal.com/FlightPDFArchive/1967/1967%20-%201679.PDF