Altera Offers Enhanced Quartus II Software Version 9.1

Altera announced the release of Quartus II software version 9.1, a software for CPLD, FPGA and HardCopy ASIC designs.

Altera stated that new features and enhancements within Quartus II software v9.1 reduce compile times 20 percent versus the previous software release, while continuing to deliver on average 2X to 3X faster compile times compared to competing high-density 40-nm and 65-nm designs. New to the software is a Rapid Recompile feature, which improves compile times for small design changes, as well as support for Altera's newly announced Cyclone IV FPGAs.

Altera said that the software provides what it termed the industry's fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually over the past five years. The compile time advantages in the latest release are driven by more efficient place and route algorithms, improved multiprocessor support and faster timing-driven synthesis.

The new Rapid Recompile feature enhances the Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes designer productivity when making small engineering change order (ECO)-style design changes after a full compile is run, reducing compilation times by 50 percent on average versus running another full compile on the design. Rapid Recompile also improves designer productivity during timing closure by preserving critical timing during late design changes.

The three smallest Cyclone IV GX devices will be supported in the Quartus II design software v9.1 with the remaining Cyclone IV devices supported in the Quartus II design software v9.1 service pack 1.

"Design teams today continue to look for ways to maximize productivity as they face the challenges of tighter budgets, shrinking R&D resources and truncated design schedules," said Chris Balough, senior director of software, embedded, and DSP marketing at Altera. "Quartus II software's increased productivity advantage ensures our customers can get their FPGAs to market quicker and with reduced engineering expenses."

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