Mentor Graphics Eyes Unification of Silicon Test and Yield Analysis

Mentor Graphics outlined its strategy and roadmap to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, low-power, mixed-signal systems-on-chip (SOCs).

As part of this strategy, Mentor is uniting its embedded compression and automatic test pattern generation (ATPG) technology with the built-in self-test (BIST) technology from recently acquired LogicVision into a new product line, called Tessent. The Tessent line is a comprehensive set of design-for-test and silicon test solutions, and also includes LogicVision's SiliconInsight product, Mentor's layout-aware diagnosis tools and the newly announced Tessent YieldInsight product to provide solutions for post-silicon test characterization and yield analysis.

"Those who follow Mentor Graphics know that we target segments where we can be in a strong number one position," said Joseph Sawicki, vice president and general manager for the Design-to-Silicon Division at Mentor Graphics. "The combination of Mentor's market-leading scan-based test and yield analysis products, and the LogicVision BIST solutions, puts us in the top spot across the board in silicon test. We plan to grow from that position of strength by taking the newly branded Tessent line broader and deeper, and continuing to provide the industry's most complete and unified solution for silicon test, diagnosis and yield analysis."

"ON Semiconductor is committed to utilizing best-in-class ATPG and BIST technologies for product development," said Peter Zdebel, senior vice president and CTO at ON Semiconductor. "We are enthusiastic about the benefits that the single integrated product line from Mentor Graphics offers. We have a longstanding relationship with Mentor in the DFT/ATPG arena that we value and will continue to foster. We look forward to utilizing Mentor's expanded silicon test and yield analysis product-line to provide our customers with world-class products."

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