Avago Provides IP to Enable Juniper Networks' Development of Silicon

Avago announced that it provided IP to Juniper Networks to enable the development of the company's silicon devices.

Avago said the new Juniper designs are part of the Junos Trio chipset that enables the delivery of Juniper's MX-3D platforms. Each device features close to 100 SerDes channels and is capable of driving a lossy backplane channel and multiple backplane connectors. In addition to exhibiting 'best-in-class' crosstalk and jitter performance, Avago's decision feedback equalization (DFE) and modular architectures enable high-density, low-power solutions, which are critical in today's demanding applications.

"Avago's multi-gigabit SerDes cores meet our stringent performance requirements," said R.K. Anand, executive VP of Foundation Technologies at Juniper Networks. "Cutting edge IP from Avago for SerDes and high-speed I/O are essential technologies that enable us to deliver solutions in silicon for our customers."

"We are committed to providing solutions that meet our customers' growing requirements for speed, density, power, and execution," said Frank Ostojic, VP and general manager of Avago's ASIC Products Division. "We are delighted that Juniper has chosen Avago to engage so closely on such breakthrough projects that enable us to showcase our embedded SerDes leadership within the industry and meet Juniper's needs of performance and scale for their new product."

Avago is a supplier of analog interface components for communications, industrial and consumer applications. By leveraging its core competencies in III-V compound and silicon semiconductor design and processing, the company provides a range of analog, mixed signal and optoelectronics components and subsystems to approximately 40,000 end customers.

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