Audio
Processing and Material Challenges to Be Met Beyond 22 nm
Tom St. Dennis, senior vice president and general manager of Applied Materials’ Silicon Systems Group, talks about developments in logic, memory and materials during this time of More than Moore.
Processing Challenges at the 32 nm Edge
Girish Dixit, vice president, worldwide process applications and field process support at Novellus Systems, talks about the challenges introduced by smaller features and new materials, as well as behavior changes of traditional elements when designed into these smaller nodes.
EDA Considers 22 nm and Looks Beyond
Joseph Sawicki, vice president and general manager for Mentor Graphics’ Design-to-Silicon Division, speaks about the technology challenges that EDA faces. “I am fundamentally an optimist,” Sawicki says. “I continue to believe that the integration density area savings that you get by going to new
ITRS Lithography Update Weeds Out 45 nm Options
Mike Lercel, lithography director at Sematech and also U.S. chair of the ITRS lithography working group, highlights the latest updates to the ITRS Lithography chapter, including changes in potential solutions and tighter CDU and overlay requirements.
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