Events
11.2 High-Level Power and Thermal Management | DATE - Design, Automation and Test in Europe
The Design, Automation, and Test in Europe (DATE) conference is the worlds premier conferences dedicated to electronic and embedded systems.
IPC Thermal Management Conference Highlights What’s Cool in Today’s Technologies and Materials | IPC
IPC Technology Interchange on Thermal Management, Nov. 3–4, 2010, will cover the latest thermal management technologies for electronics manufacturing.
Laird Technologies Thermal Management Expert to Present at AMD Technical Forum Exhibition 2010 :
Laird Technologies Thermal Management Expert to Present at AMD Technical Forum & Exhibition 2010 : Electronics News from Electronic Specifier
Submission form for a demonstration at the University Booth at DATE’10
Thermal Vias Based on Composite Materials Jörg Hertwig Technical University of Dresden Institute of Electromechanical and Electronic Design The continuous down-scaling of electronic systems into the nanoscale era presents a multitude of new design challenges. Thermal problems are one of the most
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, DMI-University of Cagliari 32 Via Ospedale, Cagliari, Italy [mulas,pittau,buttu,salvatore]@unica.it Andrea Acquaviva DI-University of Verona Strada le
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip ∗ G. M. Link, N. Vijaykrishnan The Pennsylvania State University, University Park, PA, 16802 {link,vijay}@cse.psu.edu Abstract Many existing thermal management techniques focus on reducing the overall power consumption of the
Hybrid Architectural Dynamic Thermal Management
Hybrid Architectural Dynamic Thermal Management Kevin Skadron Department of Computer Science, University of Virginia Charlottesville, VA 22904 skadron@cs.virginia.edu Abstract When an application or external environmental conditions cause a chip’s cooling capacity to be exceeded, dynamic
Post-placement Temperature Reduction Techniques
Post-placement Temperature Reduction Techniques Wei Liu, Alberto Nannarelli Technical University of Denmark Kgs.Lyngby, Denmark Andrea Calimera,Enrico Macii,Massimo Poncino Politecnico di Torino Torino, Italy Abstract—With technology scaled to deep submicron era, temperature and temperature
Microarchitectural Floorplanning under Performance and Thermal Tradeoff
Microarchitectural Floorplanning Under Performance and Thermal Tradeoff Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh † School of Electrical and Computer Engineering † College of Computing Georgia Institute of
Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip
Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip Clocking1 Chunsheng Liu and Vikram Iyengar Computer and Electronic Engineering IBM Microelectronics University of Nebraska-Lincoln 1000 River Road, Building 863B Omaha, NE 68182, USA Essex Jct, VT
