Events
Imagination Technologies Powers 3D for NXP Set Top Box platform : Electronics News from
Imagination Technologies Powers 3D for NXP Set-Top Box platform : Electronics News from Electronic Specifier
Achieving New Levels of Performance and Reduced Power - ARM
Achieving New Levels of Performance and Reduced Power Consumption in MCU Designs with ARM Cortex-M
element14: Black Box Digital Signage /iCOMPEL Demo
<div class='jive-rendered-content'><div><p class="MsoNormal"><span style="font-size: 10pt; color: black; font-family: Tahoma;">iCOMPEL demo's will now be scheduled and offered every Friday at 11am EST. <span style="text-decoration: underline;">These sessions are open</span>to any
Multimedia Applications of Multiprocessor Systems-on-Chips
Multimedia Applications of Multiprocessor Systems-on-Chips Wayne Wolf Department of Electrical Engineering Princeton University Abstract This paper surveys the characteristics of multimedia systems. Multimedia applications today are dominated by compression and decompression, but multimedia
NXP PNX847x 8x 9x worlds first ultra low power high performance set top box platform : Electronics
NXP showcases world's first ultra low-power, high performance set top box platform : Electronics News from Electronic Specifier
Freescale, ARM & Silica: i.MX51 Seminar - ARM
Be the first to get training on Freescale’s new ARM Cortex™-A8 Processors.
Performance Analysis of SoC Architectures Based on Latency-Rate Servers
Performance Analysis of SoC Architectures Based on Latency-Rate Servers Jelte Peter Vink Eindhoven University of Technology Eindhoven, the Netherlands E-mail: jelte.peter.vink@philips.com Kees van Berkel NXP Semiconductors Research Eindhoven, the Netherlands E-mail: kees.van.berkel@nxp.com
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips Srinivasan Murali CSL, Stanford University Stanford, USA smurali@stanford.edu Martijn Coenen, Andrei Radulescu, Kees Goossens Philips Research Laboratories The Netherlands
Context-Aware Performance Analysis for Efficient Embedded System Design
Context-Aware Performance Analysis for Efficient Embedded System Design Marek Jersak, Rafik Henia, Rolf Ernst Technische Universit¨ at Braunschweig Institut f¨ ur Datentechnik und Kommunikationsnetze (IDA) D-38106 Braunschweig, Germany {jersak, henia, ernst}@ida.ing.tu-bs.de Abstract Performance
SET TOP BOX SoC DESIGN METHODOLOGY at STMicroelectronics
Abstract: In this paper we will review how the IP Reuse SoC design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the
