Events
National Semiconductor to Discuss and Demonstrate PCI Express Gen 3 Repeaters at PCI SIG Developers
National Semiconductor to Discuss and Demonstrate PCI Express Gen-3 Repeaters at PCI-SIG Developers Conference : Electronics News from Electronic Specifier
A Bus Delay Reduction Technique Considering Crosstalk
A Bus Delay Reduction Technique Considering Crosstalk Kei Hirose and Hiroto Yasuura Department of Computer Science and Communication Engineering, Kyushu University Kasuga Koen 6-1, Kasuga, Fukuoka 816-8580, JAPAN E-mail: {khirose, yasuura}@c.csce.kyushu-u.ac.jp Abstract As the CMOS technology
TIMBER: Time Borrowing and Error Relaying for Online Timing Error Resilience
TIMBER: Time borrowing and error relaying for online timing error resilience Mihir Choudhury† Vikas Chandra‡ Kartik Mohanram† Robert Aitken‡ † Department of Electrical and Computer Engineering, Rice University, Houston ‡ ARM R&D, San Jose Email: † {mihir,kmram}@rice.edu ‡
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints£ Probir Sarkar Conexant Systems Newport Beach, CA 92660 probir.sarkar@conexant.com Cheng-Kok Koh ECE, Purdue University West Lafayette, IN 47907-1285 chengkoh@ecn.purdue.edu ABSTRACT We present a solution to the
Interconnect Tuning Strategies for High-Performance ICs
Interconnect Tuning Strategies for High-Performance ICs Andrew B. Kahng, Sudhakar Muddu, Egino Sarto and Rahul Sharma Silicon Graphics, Inc., Mountain View, CA 94039 fmuddu,sarto,ashug@mti.sgi.com, abk@cs.ucla.edu Abstract Interconnect tuning is an increasingly critical degree of freedom in the
A Methodology for The Characterization of Process Variation in NoC Links
A Methodology for the Characterization of Process Variation in NoC Links Carles Hern´ andez, Federico Silla, and Jos´ e Duato Universidad Polit´ ecnica de Valencia, Grupo de Architecturas Paralelas, Departamento de Inform´ atica de Sistemas Camino de Vera s/n 46022 Valencia, Espa˜ na Email:
Issues in Implementing Latency Insensitive Protocols
Issues in Implementing Latency Insensitive Protocols Mario R. Casu and Luca Macchiarulo Politecnico di Torino, Dipartimento di Elettronica, C.so Duca degli Abruzzi, 24, I-10129 Torino, Italy mario.casu@polito.it luca.macchiarulo@polito.it 1 Extended Abstract The performance of future
Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining
Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining Jingye Xu, Abinash Roy and Masud H.Chowdhury ECE, University of Illinois at Chicago, Chicago, IL60607 jxu6@uic.edu, aroy5@uic.edu, masud@ece.uic.edu Abstract This paper addresses the problem of interconnect
Stretching the Limits of FPGA SerDes for Enhanced ATE Performance
Stretching the Limits of FPGA SerDes for Enhanced ATE Performance A.M. Majid, D.C. Keezer School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA, USA Abstract – This paper describes a multi-gigahertz test module to enhance the performance capabilities of
A Novel Metric for Interconnect Architecture Performance
A Novel Metric for Interconnect Architecture Performance Parthasarathi Dasgupta‡, Andrew B. Kahng‡ ¶, and Swamy Muddu¶ ‡ CSE Department, UCSD, La Jolla, CA 92093-0114 ¶ ECE Department, UCSD, La Jolla, CA 92093-0407 partha@cs.ucsd.edu, ¡ abk, smuddu ¢@ucsd.edu Abstract We propose a new metric
