Events
Easics | DATE - Design, Automation and Test in Europe
The Design, Automation, and Test in Europe (DATE) conference is the worlds premier conferences dedicated to electronic and embedded systems.
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning Roman Lysecky, Frank Vahid* Department of Computer Science and Engineering University of California, Riverside {rlysecky, vahid}@cs.ucr.edu *Also with the Center for Embedded Computer Systems at UC Irvine Abstract In
A P1500-compatible programmable BIST approach for the test of Embedded Flash Memories
A P1500-compatible programmable BIST approach for the test of Embedded Flash Memories P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy httpwww.cad.polito.it/ Abstract In this paper we present a
Managing a Reconfigurable Processor in a General Purpose Workstation Environment
Managing a Reconfigurable Processor in a General Purpose Workstation Environment Michael Dales Department of Computing Science, University of Glasgow, 17 Lilybank Gardens, Glasgow, G12 8RZ, Scotland. michael@dcs.gla.ac.uk Abstract Reconfigurable processor hybrids are becoming an accepted solution
Fault Insertion Testing of a Novel CPLD-Based Fail-Safe Syste
Fault Insertion Testing of a Novel CPLD-based Fail-Safe System Gerhard Grießnig AVL LIST GMBH Graz, Austria gerhard.griessnig@avl.com Roland Mader, Christian Steger, Reinhold Weiß Graz University of Technology Institute for Technical Informatics (ITI) Graz, Austria rmader@sbox.tugraz.at,
Energy-delay efficient data storage and transfer architectures: circuit technology versus design
Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions Francky Catthoor, IMEC, Kapeldreef 75, Leuven, Belgium 1 Abstract Both in custom and programmable instruction-set processors for data-dominated multi-media applications, many of
Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT
Design of an Application-specific Instruction Set Processor for High-throughput and Scalable FFT Xuan Guan, Hai Lin and Yunsi Fei Dept. of Electrical & Computer Engineering University of Connecticut, Storrs, CT, USA E-mail: {xug06002,hal06002,yfei}@engr.uconn.edu Abstract—Various Orthogonal
Two-Level Microprocessor-Accelerator Partitioning
Two-Level Microprocessor-Accelerator Partitioning Abstract The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move software functions from the microprocessor to accelerators on
Automating Processor Customisation: Optimised Memory Access and Resource Sharing
Automating Processor Customisation: Optimised Memory Access and Resource Sharing Robert Dimond, Oskar Mencer and Wayne Luk Department of Computing, Imperial College, 180 Queens Gate, London. SW7 2RH {rgd00,oskar,wl}@doc.ic.ac.uk Abstract We propose a novel methodology to generate Application
Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level… or Will Software and Custom
Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level… or Will Software and Custom Processors (or System-Level Design) Extend Moore’s Law? Alan Naumann, President and CEO, CoWare® , Inc, US Abstract: The challenges of electronic design are escalating as software and embedded processors
