Events
element14: DRAM KnowHow - Open the Black Box of Memory
Was sie immer schon über Speicher wissen wollten! ... Aber niemals den richtigen
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms P. Marchal (marchal@imec.be, D. Bruni (dbruni@deis.unibo.it, J.I. Gomez (gomezjo@imec.be, *) L. Benini (lbenini@deis.unibo.it L. Piñuel (lpinuel@dacya.ucm.es F. Catthoor(catthoor@imec.be H.
System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications
System-level Power/performance Evaluation of 3D stacked DRAMs for Mobile Applications Marco Facchini12 , Trevor Carlson1 , Anselme Vignon2 , Martin Palkovic1 , Francky Catthoor1 , Wim Dehaene2 , Luca Benini3 , Paul Marchal1 1 IMEC – Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001
Increasing PCM Main Memory Lifetime
Increasing PCM Main Memory Lifetime Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem and Daniel Moss´ e Department of Computer Science, University of Pittsburgh, Pittsburgh, Pennsylvania USA {apf75,miaozhou,sab104,childers,melhem,mosse}@cs.pitt.edu Abstract The
Energy-Oriented Dynamic SPM Allocation Based on Time-Slotted Cache Conflict
Energy-oriented dynamic SPM allocation based on Time-Slotted Cache Conflict Graph WANG huan, ZHANG yang, MEI chen, LING ming National ASIC System Engineering Technology Research Center Southeast University, Nanjing 210096, China {nanqihao, tianna1121, mei.mc121}@gmail.com, trio@seu.edu.cn
A Case for Multi-Channel Memories in Video Recording
A case for multi-channel memories in video recording Eero Aho, Jari Nikara, Petri A. Tuominen, and Kimmo Kuusilinna Nokia Research Center Tampere, Finland eero.aho@nokia.com Abstract – In video recording, ever increasing demands on image resolution, frame rate, and quality necessitate a lot of
SoC Design and Test Considerations
1 of 6 Abstract: Modern SoC Design for high-volume products requires a strong focus on Design-for-Test and Designfor-Manufacturability. We present a case study of an SoC test concept, including a description of the DfT and DfM features included in the SoC device and a brief motivation for their
Embedded DRAM Architectural Trade-Offs
Embedded DRAM Architectural Trade-Offs Norbert Wehn Søren Hein University of Kaiserslautern Siemens AG Institute of Microelectronic Systems Semiconductor Group Erwin-Schr¨ odinger-Strasse Balanstraße 73 D-67663 Kaiserslautern, Germany D-81617 M¨ unchen, Germany e-mail: wehn@e-technik.uni-kl.de
Energy-delay efficient data storage and transfer architectures: circuit technology versus design
Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions Francky Catthoor, IMEC, Kapeldreef 75, Leuven, Belgium 1 Abstract Both in custom and programmable instruction-set processors for data-dominated multi-media applications, many of
An Efficient Distributed Memory Interface for Many-Core Platform with 3D Stacked DRAM
An efficient distributed memory interface for Many-Core Platform with 3D stacked DRAM Igor Loi, and Luca Benini DEIS, University of Bologna, Bologna, Italy igor.loi@unibo.it luca.benini@unibo.it Abstract—Historically, processor performance has increased at a much faster rate than that of main
