Events
Utilizing Formal Assertions for System Design of Network Processors
Utilizing Formal Assertions for System Design of Network Processors Xi Chen, Yan Luo, Harry Hsieh, Laxmi Bhuyan University of California, Riverside, CA xichen, yluo, harry, bhuyan ¡@cs.ucr.edu Felice Balarin Cadence Berkeley Laboratories, Berkeley, CA felice@cadence.com Abstract System level
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Assertion-Based Design Exploration of DVS in Network Processor Architectures Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang University of California, Riverside jiayu, wwu, xichen, harry, junyang ¡@cs.ucr.edu Felice Balarin Cadence Berkeley Laboratories felice@cadence.com Abstract With the
Queue Management in Network Processors
Queue Management in Network Processors I. Papaefstathiou1 , T. Orphanoudakis2 , G. Kornaros2 , C. Kachris2 , I. Mavroidis2 , A. Nikologiannis2 1 Foundation of Research & Technology Hellas (FORTH), Institute of Computer Science (ICS), Vassilika Vouton, GR71110, Heraklio, Crete, Greece
Microsoft Word - DemoAbstract2pages_Template-vlast2222.doc
HS-SCALE ADAPTIVE MPSOC PLATFORM Gabriel Marchesan Almeida, Sameer Varyani, Gilles Sassatelli, Lionel Torres, Pascal Benoit and Michel Robert {name.lastname}@lirmm.fr University of Montpellier 2/CNRS Montpellier Laboratory of Computer Science, Robotics and Microelectronics (LIRMM) Montpellier,
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study Matthias Gries1 , Chidamber Kulkarni1 , Christian Sauer2 , Kurt Keutzer1 1 University of California, Berkeley 2 Infineon Technologies, Corporate Research, Munich {gries, kulkarni, sauer, keutzer}@eecs.berkeley.edu
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation G. Surendra, Subhasis Banerjee, S. K. Nandy CAD Laboratory, Supercomputer Education and Research Center Indian Institute of Science, Bangalore 560012, India Email: {surendra@cadl,
An ILP Formulation for System-Level Application Mapping on Network Processor Architectures
An ILP Formulation for System-Level Application Mapping on Network Processor Architectures1 Chris Ostler and Karam S. Chatha, {chrisost, kchatha}@asu.edu Department of CSE, Arizona State University, Tempe, AZ 85287. Abstract Current day network processors incorporate several architectural
NPSE: A High Performance Network Packet Search Engine
NPSE: A High Performance Network Packet Search Engine Naresh Soni, Nick Richardson, Lun-Bin Huang, Suresh Rajgopal, George Vlantis STMicroelectronics, 4690 Executive Drive, San Diego, 92121 CA, U.S.A. naresh.soni@st.com, nick.richardson@st.com, lun-bin.huang@st.com, suresh.rajgopal@st.com,
40Gbps De-Layered Silicon Protocol Engine for TCP Record
40Gbps De-Layered Silicon Protocol Engine for TCP Record H.Shrikumar Ipsil Inc., Cambridge MA, shri@ipsil.com Abstract We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned
An Interprocedural Code Optimization Technique for Network Processors Using Hardware
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support Hanno Scharwaechter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Integrated Signal Processing Systems RWTH Aachen University Aachen, Germany Abstract Sophisticated C
