Events
9.7 Physical Design Potpourri: DFM, Delay Modelling and Floorplanning | DATE - Design, Automation
The Design, Automation, and Test in Europe (DATE) conference is the worlds premier conferences dedicated to electronic and embedded systems.
Creating Value Through Test
Creating Value Through Test Erik Jan Marinissen½ Bart Vermeulen½ Robert Madge¾ Michael Kessler¿ Michael M¨ uller¿ ½ Philips Research Laboratories IC Design – Digital Design & Test Prof. Holstlaan 4 – WAY-41 5656 AA Eindhoven The Netherlands erik.jan.marinissen@philips.com
Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits
Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits Peter Wilson and Reuben Wilcock Electronics System Design Group, School of Electronics and Computer Science University of Southampton, UK {prw,rw3}@ecs.soton.ac.uk Abstract This paper describes a systematic
Yield Improvement and Repair Trade-Off For Large Embedded Memories
Yield Improvement and Repair Trade-Off For Large Embedded Memories Yervant Zorian LogicVision, Inc., San Jose, California, USA zorian@logicvision.com Abstract In this paper, we give an overview of the trade-off to improve yield and optimize silicon manufacturing cost. The specific technology
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement In the Presence of Intra-Die Variations Tom W. Chen System VLSI Technology Organization Hewlett Packard Co., Fort Collins, CO Justin Gregg Dept. of Electrical and Computer
Double-Via-Driven Standard Cell Library Design
Double-Via-Driven Standard Cell Library Design Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin Computer Science and Engineering Department Yuan Ze University, Chung-Li, Taiwan csrlin@cs.yzu.edu.tw Abstract Double-via placement is important for increasing chip manufacturing yield.
DFM/DFY Design for Manufacturability and Yield – Influence of Process Variations in Digital, analog
DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design Organizers: A. Ripp, MunEDA GmbH, Munich, Germany – andreas.ripp@muneda.com;, M. Bühler, IBM Deutschland Entwicklung GmbH, Böblingen,
Synthesis for Manufacturability: a Sanity Check
Synthesis for Manufacturability: a Sanity Check ∗ Alessandra Nardi Alberto L. Sangiovanni-Vincentelli EECS Department, University of California at Berkeley, Berkeley, CA 94720 {nardi,alberto}@eecs.berkeley.edu Abstract As we move towards nanometer technology, manufacturing problems become
A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash
A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories Pierluigi Daglio STMicroelectronics – Agrate Brianza – Milan – Italy E-mail: pierluigi.daglio@st.com Abstract Today almost all the people in the industry are talking widely about full
Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance
1 Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance Tong-Yu Hsieh and Kuen-Jong Lee Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan 70101 E-mail: kjlee@mail.ncku.edu.tw Melvin A. Breuer Department of Electrical Engineering
