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IBM Tivoli User Community - Events
Tivoli User Group (TUG) community provides strong linkages between customers and other participants allowing for exchange of ideas, gaining product knowledge, collaboration, networking, education, certification, discussion forums in various products like Tivoli Monitoring, Storage Manager, Tivoli
Parametric Built-In Self-Test of VLSI Systems
Parametric Built-In Self-Test of VLSI Systems D. Niggemeyer, M. Rüffer1 Laboratory for Information Technology University of Hannover, Germany niggemeyer@lfi.uni-hannover.de Abstract Conventionally, Automatic Test Equipment (ATE) has been used for parametric tests of VLSI systems to determine the
Test Resource Partitioning: a Design & Test Issue
Test Resource Partitioning: a Design & Test Issue J.P. Teixeira1 , I.M. Teixeira1 , C.E. Pereira2 , O.P. Dias1 , J. Semião1 , 1 IST / INESC, R. Alves Redol, 9, 1000-029 Lisboa, Portugal 2 UFRGS, Porto Alegre, Brazil jct@inesc.pt ABSTRACT Product development economics and specs drive the need for
Using Mission Logic for Embedded Testing
Using Mission Logic for Embedded Testing Rainer Dorsch Hans-Joachim Wunderlich Computer Architecture Lab, University of Stuttgart, D-70565 Stuttgart, Germany {rainer.dorsch,wu}@informatik.uni-stuttgart.de Abstract Testing logic cores of a system-on-a-chip causes a high test data volume which has
SoC Design and Test Considerations
1 of 6 Abstract: Modern SoC Design for high-volume products requires a strong focus on Design-for-Test and Designfor-Manufacturability. We present a case study of an SoC test concept, including a description of the DfT and DfM features included in the SoC device and a brief motivation for their
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Re-Examining the Use of Network-on-Chip as Test Access Mechanism Feng Yuan, Lin Huang and Qiang Xu Department of Computer Science & Engineering The Chinese University of Hong Kong, Shatin, N.T., Hong Kong Email: {fyuan,lhuang,qxu}@cse.cuhk.edu.hk Abstract Existing work on testing NoC-based
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications D.C. Keezer1 , D. Minier2 , P. Ducharme2 1- Georgia Institute of Technology, Atlanta, Georgia USA 2 – IBM, Bromont, Canada Abstract The ability to precisely control the timing of digital signals
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL D.C. Keezer, C. Gray, A. Majid, N. Taher Georgia Institute of Technology School of Electrical and Computer Engineering, Atlanta, GA Abstract This paper describes two research projects that develop new low-cost techniques for testing
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips Sandeep Kumar Goel Erik Jan Marinissen Philips Research Laboratories IC Design – Digital Design & Test Prof. Holstlaan 4, M/S WAY-41 5656 AA Eindhoven, The Netherlands SandeepKumar.Goel, Erik.Jan.Marinissen
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression Mohammad Tehranipour, Mehrdad Nourani Center for Integrated Circuits & Systems The Univ. of Texas at Dallas Richardson, TX 75083 mht021000,nourani ¡@utdallas.edu Krishnendu
