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JTAG Test and Programming
Easy to use tools for JTAG Testing and In-System Programming
Quad Power Managers Pack Programmable Delay And Watchdog Timers
News | www.eepn.com | 17 hours 20 minutes ago
Virtual system integration and simulation
News | www.electroline.com.au | Nov 20, 2009
Embedded and electronic system design teams face the challenge of reducing development time and costs while improving quality, performance and functionality. However, increased system complexity is raising the cost of verification, in some cases to as much as 70% of the overall project cost.
Test Design Studio Maintenance Release (Build 4530) - Patterson Consulting
News | www.patterson-consulting.net | Nov 16, 2009
Maintenance Release We are pleased to annouce that a new maintenance release of Test Design Studio 2.0 is now available (Build 4530).
JTAG Technologies offers free boundary scan tool
News | www.electronicsweekly.com | Nov 11, 2009
"This marks a fundamental change in our approach to the market. We are making boundary scan more accessible and crucially more affordable," said James Stanbridge, UK sales manager at JTAG Technologies
Application note: MIMO in LTE Operation/Measurement -- Excerpts on LTE Test
Press Release | www.home.agilent.com | Nov 4, 2009
Agilent is committed to helping you understand MIMO technology so you can get your products to market fast. We will provide you with the design and test solutions you need, when you need them. So, as you take MIMO forward, Agilent clears the way.
https://www.home.agilent.com/agilent/editorial.jspx?cc=US&lc=eng&ckey=1498754&id=1498754&cmpid=1151
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Mentor Graphics reveals new strategy to unify silicon test and yield analysis
Press Release | www.edadesignline.com | Nov 4, 2009
Mentor Graphics Corporation has outlined its new strategy to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, low-power, mixed-signal systems-on-chip (SOCs).
http://www.edadesignline.com/221600201?cid=RSSfeed_EDAdesignline_edadlALL
ASSET's ScanWorks supports PLX Technology's PCI Express switch family's visionPAK diagnostic toolset
News | www.Embedded-Computing.com | Nov 4, 2009
ASSET(r) InterTech, the leading supplier of open tools for embedded instrumentation for design validation, test and debug, and PLX Technology, Inc. (NASDAQ: PLXT), the leading global supplier of PCI Express(r) (PCIe(r)) switch and bridge silicon, today announced that ASSET's ScanWorks(r) platform
http://www.Embedded-Computing.com/news/Technology+Partnerships/19673
Juniper Networks Completes World’s First Network Instruction Set Processor Design Using Mentor Graphics Calibre and Design-for-Test Solutions (Mentor Graphics)
News | www.mentor.com | Nov 4, 2009
processor IC using Mentor Graphics® physical verification and silicon test tools.
Strategic Relationship with SiliconAid Extends ASSET’s ScanWorks Platform into Chip Test and Verification
News | www10.EDACafe.com | Nov 4, 2009
Chip Debugger Will Be Integrated into ScanWorks®; ASSET to Resell IEEE P1687 Insertion and Verification Tools
http://www10.EDACafe.com/nbc/articles/view_article.php?articleid=757504
ASSET’s ScanWorks supports PLX Technology’s PCI Express switch family’s visionPAK diagnostic toolset
Press Release | www.edn.com | Nov 4, 2009
Richardson, TX (Nov. 4, 2009) – ASSET® InterTech, the leading supplier of open tools for embedded instrumentation for design validation, test and debug, and PLX Technology, Inc.
