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by A. K. Nanda A.-T. Nguyen M. M. Michael D. J. Joseph Highthroughput coherence control and...
by A. K. Nanda A.-T. Nguyen M. M. Michael D. J. Joseph Highthroughput coherence control and hardware messaging in Everest Everest is an architecture for high-performance cache coherence and message passing in partitionable distributed shared-memory systems that use commodity shared
wow.dvi
WOW: Wise Ordering for Writes – Combining Spatial and Temporal Locality in Non-Volatile Caches Binny S. Gill and Dharmendra S. Modha IBM Almaden Research Center, 650 Harry Road, San Jose, CA 95120 Emails: {binnyg,dmodha}@us.ibm.com Abstract— Write caches using fast, non-volatile storage are now
Libra: A Library Operating System for a JVM in a Virtualized Execution Environment Glenn Ammons IBM...
Libra: A Library Operating System for a JVM in a Virtualized Execution Environment Glenn Ammons IBM T.J. Watson Research Center ammons@us.ibm.com Jonathan Appavoo IBM T.J. Watson Research Center jappavoo@us.ibm.com Maria Butrico IBM T.J. Watson Research Center butrico@us.ibm.com Dilma Da Silva
nguyen.dvi
High-Throughput Coherence Controllers Ashwini K. Nanday , Anthony-Trung Nguyenz , Maged M. Michaely , and Douglas J. Josephy y IBM Research z University of Illinois, Urbana-Champaign Thomas J. Watson Research Center Department of Computer Science Yorktown Heights, NY 10598 Urbana, IL 68101
Dynamic Compilation: The Benefits of Early Investing Prasad Kulkarni Florida State University IBM...
Dynamic Compilation: The Benefits of Early Investing Prasad Kulkarni Florida State University IBM T.J. Watson Research Center kulkarni@cs.fsu.edu Matthew Arnold Michael Hind IBM T.J. Watson Research Center {marnold,hindm}@us.ibm.com Abstract Dynamic compilation is typically performed in a separate
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Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors Maged M. Michael, Ashwini K. Nanda, and Beng-Hong Lim AbstractÐScalable distributed shared-memory architectures rely on coherence controllers on each processing node to synthesize cache-coherent shared memory across
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors Maged M....
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors Maged M. Michael Ashwini K. Nanda IBM Research Thomas J. Watson Research Center Yorktown Heights, NY 10598 fmichael,ashwinig@watson.ibm.com Abstract Recent research shows that the occupancy of the coherence
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors Maged M. Michaely ,...
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors Maged M. Michaely , Ashwini K. Nandaz , Beng-Hong Limz , and Michael L. Scotty y University of Rochester z IBM Research Department of Computer Science Thomas J. Watson Research Center Rochester, NY 14627 Yorktown Heights,
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