Whitepapers
TechOnline | Using HDL Designer to Facilitate DO-254 Compliant and Safety-Critical Design Processes
This paper describes the DO-254 compliance considerations for HDL coding and Detailed Design as well as other related processes.
TechOnline | IEEE Std VHDL 1076.1-1999: The Analog and Mixed-Signal Extensions for VHDL
Analog and mixed-signal designers have long lacked what their digital colleagues have enjoyed for a decade: standard hardware description languages that allow portability of models between different
TechOnline | Binding SystemVerilog to VHDL Components Using Questa
Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVeril
TechOnline | SystemVision for Embedded Mechatronic Systems: Hardware Modeling
This paper will discuss how the IEEE standard VHDL-AMS language can be used to describe the behavior of the heterogeneous hardware technologies typically present in embedded mechatronic systems. Syst
TechOnline | As In AOP So In OOP: A Transition Guide to SystemVerilog for the eUser
For e users, Aspect Oriented Programming (AOP) is a known, good mechanism for
TechOnline | Is SystemVerilog Only for System-Level Design
SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of
TechOnline | Planning SystemVerilog Adoption
This paper provides a new way for digital design and verification groups to easily adopt SystemVerilog. The paper opens with a historical review of how transaction-level modeling (TLM) has been used for design, followed by an explanation of how SystemVerilog can be useful for taking verification to
TechOnline | Achieving Timing Closure with Bluespec SystemVerilog
Achieving timing closure becomes increasingly difficult with more aggressive technologies at higher clock speeds. In this document we describe some of the techniques used by the Bluespec SystemVerilog (BSV) designer to achieve timing closure. Most of them will be quite familiar to the RTL designer,
TechOnline | Overview of Digital Design with Verilog HDL
Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective of Verilog rather than emphasizing o
TechOnline | Is There a Future for SystemVerilog Interfaces?
In this paper we argue that the SystemVerilog interface construct is inadequately specified, insufficiently powerful for real applications, and impossible to implement consistently in its current form.
